《KeyStone Overview》.pdfVIP

KeyStone C66x Multicore SoC Overview Dec, 2011 Outline • Multicore Challenge • KeyStone Architecture • Reminder About KeyStone Solution Challenge Before KeyStone • Multicore performance degradation • Lack of efficient multicore communication • Not easy to program the high speed IO • Relatively high loading for EMAC driver • Lack of efficient multicore debug tool • Any other …… Outline • Multicore Challenge • KeyStone Architecture • Reminder About KeyStone Solution KeyStone Device Features C66x CorePac – 1 to 8 C66x Fixed/Floating-Point CorePac DSP Cores at up to 1.25 GHz – Backward-compatible with C64x+ and C67x+ cores Application-Specific Memory Subsystem – Fixed and Floating Point Operations Coprocessors 64-Bit MSM – RSA instruction set extensions DDR3 EMIF SRAM – Chip-rate processing (downlink uplink) MSMC – Reed-Muller decoding (CorePac 1 and 2 only) Memory Subsystem Debug Trace – Up to 1 MB Local L2 memory per core Boot ROM – Up to 4 MB Multicore Shared Memory (MSM) – Multicore Shared Memory Controller (MSMC) Semaphore C66x™