《Wafer level packaging of MEMS》.pdf

IOP PUBLISHING JOURNAL OF MICROMECHANICS AND MICROENGINEERING J. Micromech. Microeng. 18 (2008) 073001 (13pp) doi:10.1088/0960-1317/18/7/073001 TOPICAL REVIEW Wafer level packaging of MEMS Masayoshi Esashi The World Premier International Research Center Advanced Institute for Materials Research, Tohoku University, Sendai, Japan E-mail: esashi@cc.mech.tohoku.ac.jp Received 7 September 2007, in final form 26 March 2008 Published 29 May 2008 Online at /JMM/18/073001 Abstract Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review. (Some figures in this article are in colour only in the electronic version) 1. Introduction MEMS and eliminate extra packaging equipment. Common technologies needed for wafer level packaging are also used Packaging for MEMS (micro electro mechanical systems), for mak