《22 Flip Chip Packaging for Nanoscale Silicon Logic Devices- Challenges and Opportunities》.pdf

Chapter 22 Flip Chip Packaging for Nanoscale Silicon Logic Devices: Challenges and Opportunities Debendra Mallik(*ü ), Ravi Mahajan, and Vijay Wakharkar 22.1 Introduction After decades of following the roadmap laid out by Moore’s law [1] , silicon features have reached the nanoscale, which is below 100 nm in dimension, as illustrated in Fig. 22.1 . The first logic products with 90-nm transistors, using the traditional silicon dioxide insulator and polysilicon gate, went into volume production in 2003. More recently in 2007, 45-nm devices using a revolutionary high-k metal gate transistor technology have been introduced [2 , 3] . These nanoscale devices enable higher per- formance circuits, which in turn drive advanced features in their packaging. These devices can significantly lower the power consumption of high-performance logic products creating new applications in the fast-growing ultramobile market (Fig. 22.2 ) and thus requiring packaging to support the demands of these form factors. This chapter will discuss the challenges and opportunities in flip chip packaging for these nanoscale devices. In the early days of the semiconductor industry, microelectronics packaging pri- marily provided space transformation, and structural and environmental protection of the small but expensive integrated circuit (IC) devices so that they could be con- nected to relatively large electronic system boards. The role of microelectronics packaging has continued to expand over the past few decades to include electrical and thermal performance management, as well as enabling syste