《Material and process limits in silicon VLSI technology 》.pdf

Material and Process Limits in Silicon VLSI Technology JAMES D. PLUMMER, FELLOW, IEEE, AND PETER B. GRIFFIN Invited Paper The integrated circuit (IC) industry has followed a steady path of shrinking device geometries for more than 30 years. It is widely be- lieved that this process will continue for at least another ten years. However, there are increasingly difficult materials and technology problems to be solved over the next decade if this is to actually occur and, beyond ten years, there is great uncertainty about the ability to continue scaling metal–oxide–semiconductor field-effect transistor (MOSFET) structures. This paper describes some of the most chal- lenging materials and process issues to be faced in the future and, where possible solutions are known, describes these potential solu- tions. The paper is written with the underlying assumption that the basic metal–oxide–semiconductor (MOS) transistor will remain the dominant switching device used in ICs and it further assumes that silicon will remain the dominant substrate material. Keywords—Dielectric materials, MOSFETs, semiconductor de- vice doping, semiconductor device fabrication, silicon. I. INTRODUCTION Fig. 1. Feature size versus time in silicon ICs. For more than 30 years, the integrated circuit (IC) industry has followed a steady path of constantly shrinking device all this has happened has led to an expectation that faster and geometries and increasing chip size. This strategy has been more powerful chips will continue to be introduced on the driven by the increased performance that smaller devices same schedule for the foreseeable future. In fact, the semi- make possible and the increased functionality that larger conductor industry itself has developed a “roadmap” based chips provide. Together, these performance