《IS61NLP51236》.pdf

IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 ® IS61NLP102418/IS61NVP102418 ISSI 256K x 72, 512K x 36 and 1M x 18 JULY 2006 18Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES DESCRIPTION • 100 percent bus utilization The 18 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide • No wait cycles between Read and Write a burstable, high-performance, no wait state, device for • Internal self-timed write cycle networking and communications applications. They are • Individual Byte Write Control organized as 256K words by 72 bits, 512K words by 36 bits and 1M words by 18 bits, fabricated with ISSIs • Single R/W (Read/Write) control pin advanced CMOS technology. • Clock controlled, registered address, Incorporating a no wait state feature, wait cycles are data and control eliminated when the bus switches from read to write, or • Interleaved or linear burst sequence control using write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs MODE input