Computer-AidedVerificationofElectronicCircuitsand.pptVIP

Computer-Aided Verification of Electronic Circuits and Systems EE219A – Fall 2002 Professor: Prof. Alberto Sangiovanni-Vincentelli Instructor: Alessandra Nardi Administration Office Hours: Th: 11.30-13.00 in 545H Course mailing list: send e-mail to nardi@ Course website: /~nardi/EE219A Grading Grading will be assigned on: Project (? 50% ) Homework (? 20% ) Midterm (? 30% ) There will be approximately 5 bi-weekly homework and a take-home midterm No final Projects Groups of 2 people are strongly recommended Tentative schedule: Make your choice by October 21 First update: October 31 Second update: November 21 Final presentation: December 3 and 5 May be shared with other classes you are taking Major Verification Tasks Functional Verification Specification Validation: Are the specifications consistent? Are they complete, i.e. if the design satisfies them are we sure that it is correct? Design Verification: Is the “entry” level description of my design correct? Most common reason for chip failure. Implementation Verification: Are the different levels of abstractions generated by the design process equivalent? Multi-Million-Gate Verification Moore’s Law Faster and more complex designs Test-vector size grows even faster than design size Time-to-market pressures will certainly not abate Clearly conflicts with the need to exhaustively verify a design before sign-off Digital Systems Verification Hierarchy Verification Techniques Simulation (FT): Build a mathematical model of the components of the design, submit test vectors and solve the equations that give the output as a function of the input and of the models on a computer Formal Verification (F): Prove mathematically that: A description has a set of properties Two descriptions at different levels of abstraction are functionally equivalent Verification Techniques Static Timing Analysis (T): Analyze circuit’s topological paths and check their timing properties and their impact on circuit delay Emulation (