《Block Alignment in 3D Floorplan》.pdfVIP

Block Alignment in 3D Floorplan Using Layered TCG Jill H.Y. Law Evangeline F.Y. Young Royce L.S. Ching Department of CSE Department of CSE Department of CSE Chinese University of Hong Chinese University of Hong Chinese University of Hong Kong Kong Kong hylaw@cse.cuhk.edu.hk fyyoung@cse.cuhk.edu.hk lsching@cse.cuhk.edu.hk ABSTRACT the modules are actually not 3-dimensional. The authors of [1] In modern IC design, the number of long on-chip wires proposed a slicing tree structure representation for multi-layer has been growing rapidly because of the increasing floorplans. Similar to 2D floorplan, a slicing tree is constructed for 3D floorplan. There are three kinds of internal nodes, ‘H’, circuit complexity. Interconnect delay has dominated over gate delay as technology advances into the deep ‘V’, and ‘Z’ representing horizontal, vertical, and lateral cuts submicron era. 3D chip is a feasible solution to these respectively, and each leaf is labelled by a module name. To problems. It has been shown that interconnect lengths realize a floorplan, the slicing tree has to be broken down. Each can be greatly reduced in 3D ICs. In this paper, a novel layer is represented by a slicing sub-tree. This is done by re- 3D floorplan representation namely Laye