combinational test generation for acyclic sequential circuits.pptVIP

下载本文档

3
0
约 22页
2016-03-05 发布于广东
举报
版权申诉

combinational test generation for acyclic sequential circuits.ppt

1、本文档共22页，可阅读全部内容。
2、原创力文档（book118）网站文档一经付费（服务费），不意味着购买了该文档的版权，仅供个人/单位学习、研究之用，不得用于商业用途，未经授权，严禁复制、发行、汇编、翻译或者网络传播等，侵权必究。
3、本站所有内容均由合作方或网友上传，本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺！文档内容仅供研究参考，付费前请自行鉴别。如您付费，意味着您自己接受本站规则且自行承担风险，本站不退款、不进行额外附加服务；查看《如何避免下载的几个坑》。如果您已付费下载过本站文档，您可以点击这里二次下载。
4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等，请点击“版权申诉”（推荐），也可以打举报电话：400-050-0827(电话支持时间：9:00-18:30)。
5、该文档为VIP文档，如果想要下载，成为VIP会员后，下载免费。
6、成为VIP后，下载本文档将扣除1次下载权益。下载后，不支持退款、换文档。如有疑问请联系我们。
7、成为VIP后，您将拥有八大权益，权益包括：VIP文档下载权益、阅读免打扰、文档格式转换、高级专利检索、专属身份标志、高级客服、多端互通、版权登记。
8、VIP文档为合作方或网友上传，每下载1次，网站将根据用户上传文档的质量评分、类型等，对文档贡献者给予高额补贴、流量扶持。如果你也想贡献VIP文档。上传文档

combinational test generation for acyclic sequential circuits

Oct. 5, 2001 Agrawal, Kim and Saluja Partial Scan Design With Guaranteed Combinational ATPG Vishwani D. Agrawal Agere Systems Processor Architectures and Compilers Research Murray Hill, NJ 07974 va@ Yong C. Kim and Kewal K. Saluja University of Wisconsin, Dept. of ECE Madison, WI 53706 kimy@ and saluja@ October 5, 2001 Problem Statement Overview 1. Combinational ATPG for general acyclic circuits Background: Previous results and relevant ideas Balanced model for combinational ATPG Single-fault model for multiple-faults Results 2. Special subclasses of acyclic circuits Background: Definitions and ATPG properties Examples Results 3. Conclusion Previous Work: ATPG Models for Acyclic Sequential Circuits Iterative array model (Putzolu and Roth, IEEETC, 1971) Duplicated fan-in logic model (Miczo, 1986) Duplicated logic model (Kunzmann and Wunderlich, JETTA, 1990) Balanced structure (Gupta, et al., IEEETC, 1990) Pseudo-combinational model (Min and Rogers, JETTA, 1992) Two Relevant Results Theorem (Bushnell and Agrawal, 2000): A test for a testable non-flip-flop fault in a cycle-free (acyclic) circuit can always be found with at most dseq+1 time-frames. Balanced circuit (Gupta, et al., IEEETC, 1990): An acyclic circuit is called balanced if all paths between any pair of nodes have the same sequential depth. A combinational ATPG procedure guarantees a test for any testable fault in a balanced circuit. An Example A Combinational ATPG System for General Acyclic Sequential Circuits A Single-Fault Model for a Multiple-Fault Proof of Correctness Acyclic Circuit Comb. ATPG Example ISCAS ’89 Benchmark Circuit: S5378 Acyclic Partial-Scan ISCAS’89 Circuits:Test Generation Results Acyclic Partial-Scan ISCAS’89 Circuits:Circuit Statistics Background: Subclasses of Acyclic Circuits Examples of Acyclic Subclasses Number of Scan FFs for Acyclic Subclasses Comb. ATPG Coverages for Acyclic Subclasses ATPG CPU Seconds for Acyclic Subclasses Test Lengths for Acyclic Subclasses Co