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a case for fame fpga architecture strongmodelstrong execution
A Case for FAME: FPGA Architecture Model Execution
´
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanovic, David Patterson
The Parallel Computing Laboratory
CS Division, EECS Department, University of California, Berkeley
{xtan,waterman,hcook,slbird,krste,pattrsn}@
ABSTRACT choice for the early stages of research exploration. In addi-
Given the multicore microprocessor revolution, we argue tion, when uniprocessor performance was doubling every 18
that the architecture research community needs a dramatic months, simulation speed correspondingly doubled every 18
increase in simulation capacity. We believe FPGA Archi- months without any special programming effort.
tecture Model Execution (FAME) simulators can increase The recent abrupt transition to multicore architectures [5,
the number of useful architecture research experiments per 19], however, has both increased the complexity of the sys-
day by two orders of magnitude over Software Architec- tems architects want to simulate and removed the straight-
ture Model Execution (SAME) simulators. To clear up forward path to simulator performance scaling. Parallel ap-
misconceptions about FPGA-based simulation methodolo- plications exhibit more complex behaviors than sequential
gies, we propose a FAME taxonomy to distinguish the cost- ones, including timing-dependent non-deterministic execu-
performance of variations on these ideas. We de
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