华北电力大学科技学院EDA试验代码.docVIP

实验一 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY half_adder IS PORT(a:IN STD_LOGIC; b:IN STD_LOGIC; s:OUT STD_LOGIC; c:OUT STD_LOGIC); END ENTITY half_adder ; ARCHITECTURE rtl OF half_adder IS BEGIN s=a XOR b; c=a AND b; END ARCHITECTURE rtl; 实验二 1 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY d_ff IS PORT( d:IN STD_LOGIC; clk:IN STD_LOGIC; q:OUT STD_LOGIC); END ENTITY d_ff; ARCHITECTURE rt1 OF d_ff IS BEGIN PROCESS(clk) IS BEGIN IF clkEVENT AND clk=1 THEN q=d; END IF; END PROCESS; END ARCHITECTURE rt1; 2 LIBRARY I