数字电子技术(课件)lec19.pptVIP

* Chapter 8 Counters * A Mod-100 Counter Using Two Decade Counters Lecture 19: Mealy Sequential Logic Design * Chapter 8 Counters * Three Cascaded Decade Counters Lecture 19: Mealy Sequential Logic Design Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide-by-10 and divide-by-100 outputs. * Chapter 8 Counters * Cascading Calculation Examples Lecture 19: Mealy Sequential Logic Design Determine the overall modulus of the two cascaded counter configurations below. Solution: The overall modulus for figure (a) is 8 X 12 X 16 = 1536 The overall modulus for figure (b) is 10 X 4 X 7 X 5 = 1400 * Chapter 8 Counters * Cascading Example Lecture 19: Mealy Sequential Logic Design Use 74F162 decade counter to obtain a 10 kHz waveform from a 1MHz clock. Show the logic diagram. How many decade counters is needed? Two * Chapter 8 Counters * Cascaded Counters with Truncated Sequences Lecture 19: Mealy Sequential Logic Design If these counters were cascaded in a full-modulus arrangement, what is the modulus? 216=65536 If counters don’t start counting from zero, instead they start counting from some preset number, then the modulus will vary depending on the preset number. what is the modulus for the above arrangement? 40,000 65536 – 25536 = 40000 * Chapter 8 Counters * Counter Decoding Lecture 19: Mealy Sequential Logic Design The technique is used to determine when the counter is in a certain binary state in its sequence. For example, to decode binary state 6 (110) of a 3-bit binary counter, we can use Q2=1, Q1=1, Q0=0 signals in the following manner: A HIGH appears on the output of the decoding gate, indicating that the counter is at state 6. * Chapter 8 Counters * Counter Decoding Illustration Example Lecture 19: Mealy Sequential Logic Design Implement the decoding of binary state 2 and binary state 7 of a 3-bit synchronous counter. Show the entire counter timing diagram and the output waveforms of the decoding gates. Solution: *