EDA技术P3-VHDL简介教案解析.pptVIP

课堂练习：相位检测 课堂练习：相位检测 ENTITY pd IS PORT ( A, B : IN STD_LOGIC; START : OUT STD_LOGIC; STOP : OUT STD_LOGIC ); END ENTITY pd; ARCHITECTURE rtl OF pd IS BEGIN START = A OR B; STOP = A AND B; END ARCHITECTURE rtl; 矢量信号处理 3.5 Handling multi-bit signals LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY orgate IS PORT ( a, b: IN STD_LOGIC_VECTOR (0 TO 3) ; c: OUT STD_LOGIC_VECTOR (0 TO 3) ); END ENTITY orgate; ARCHITECTURE number OF orgate IS BEGIN c = a OR b; END ARCHITECTURE number; 也可： c(0) = a(0) or b(0); c(1) = a(1) or b(1); c(2) = a(2) or b(2); c(3) = a(3) or b(3); 或： （3 DOWNTO 0) 矢量信号处理 3.5 Handling multi-bit signals ARCHITECTURE number OF orgate IS BEGIN c (0 to 3) = a(0 to 3) OR b(0 to 3); END ARCHITECTURE number; The VHDL tools will know that a, b and c are four bit wide, and therefore infer the appropriate operation for each of the bit position. If we preferred, we could write this VHDL工具已知a、b和c都是4位位宽，据此为每一位推算合理操作。如首选，我们应这样写： This is effectively a loop,which makes four assignment, one for each of the four bit positions 0,1,2 and 3. 这是一高效的循环语句，做4次赋值，每次为0、1、2、3中的一位赋值。 矢量信号处理 3.5 Handling multi-bit signals 2. STD_LOGIC_VECTOR values The value of an STD_LOGIC is indicated by a 0, 1, X or U enclosed in single quotes. Assignment statement is: a = ’1’; The value of an STD_LOGIC_VECTOR is indicated by a string of values enclosed in double quotes. Assignment statement is: a = ”1110”; 标准逻辑矢量 值 标准逻辑STD_LOGIC的值用单引号括起来的0、1、X 或 U表示。赋值语句是： 标准逻辑矢量STD_LOGIC的值用双引号括起来的数值串表示。赋值语句是： a = X”1”; 16进制表示方式 2进制表示方式 对应a(0) 对于a: STD_LOGIC_VECTOR(0 TO 3) 矢量信号处理 3.5 Handling multi-bit signals 3. Aggregates Another way to specify the value of a STD_LOGIC_VECTOR is to use an aggregate. An aggregate is a group values, separated by commas. a = ( 1,1,1,0); 集合体 另外一种指定标准逻辑矢量STD_LOGIC_VECTOR的值的方法是使用集合体。一个集合体是用逗号隔开的数值。 a = ”1110”; 使用 集合体 对应a(0) 对于a: STD_LOGIC_VECTOR(0 TO 3) 矢量信号处理 3.5 Handling mul