Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs.pdfVIP

Hindawi Publishing Corporation International Journal of Reconfigurable Computing Volume 2009, Article ID 703267, 14 pages doi:10.1155/2009/703267 Research Article Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs 1 ´ 1 2 1 Gabriel Caffarena, Juan A. Lopez, Gerardo Leyva, Carlos Carreras, and Octavio Nieto-Taladriz1 1 Departamento de Ingenierıa Electronica, Universidad Politecnica de Madrid, Ciudad Universitaria s/n, 28040 Madrid, Spain ´ ´ ´ 2 Departamento de Sistemas Electronicos, Universidad Autonoma de Aguascalientes, Ciudad Universitaria s/n, ´ ´ 20100 Aguascalientes, Mexico Correspondence should be addressed to Gabriel Caffarena, gabriel@die.upm.es Received 25 February 2009; Accepted 28 August 2009 Recommended by Cesar Torres We address the automatic synthesis of DSP algorithms using FPGAs. Optimized fixed-point implementations are obtained by means of considering (i) a multiple wordlength approach; (ii) a complete datapath formed of wordlength-wise resources (i.e., functional units, multiplexers, and registers); (iii) an FPGA-wise resource usage metric that enables an efficient distribution of logic fabric and embedded DSP resources. The paper shows (i) the benefits of applying a multiple wordlength approach to the implementation of fixed-point datapaths and (ii) the benefits of a wise use of embedded FPGA resources. The use of a complete fixed-point datapath leads to improvements up to 35%. And, the wise mapping of operations to FPGA resources (logic fabric and embedded blocks), thanks to the propose