变采样周期锁相环的分析和设计.pdfVIP

38 卷 9 期 电 网 技 术 Vol. 38 No. 9 20 14 年9 月 Power System Technology Sep. 20 14 文章编号：1000-3673 （20 14）09-2605-06 中图分类号：TM 71 文献标志码：A 学科代码：470 4051 变采样周期锁相环的分析与设计 张晓蕊，许津铭，钱强，谢少军 （南京航空航天大学 自动化学院，江苏省 南京市 2 10016 ） Analysis and Design on Variable Sampling Period Phase-Locked Loops ZHANG Xiaorui, XU Jinming, QIAN Qiang, XIE Shaojun (College of Automatic Engineering, Nanjing University of Aeronautics Astronautics, Nanjing 2 10016, Jiangsu Province, China) ABSTRACT: In existing literatures relevant to variable 的目的，在电网电压对称、无畸变的情况下可以很 sampling period phase-locked loop (VSP_PLL) the principle [4-5] 好地锁相。针对电网电压存在不平衡或畸变 的问 analysis is unsatisfactory and the design approach of its 题，大量文献研究了 SRF_PLL 的改进方法。采用 controller is not yet given. Through the comparison of 全通滤波器(all pass filter，APF)[6]可对不平衡电网 VSP_PLL with traditional synchronous reference frame based PLL, the control mechanism of VSP_PLL is clarified, and the 进行相序分离，但这种方法的频率适应性差。改进 internal relation between them is revealed. A Z-domain 型数字锁相环(enhanced PLL，EPLL)[7-8] 、双同步旋 mathematical model of VSP_PLL is established and the loop 转坐标系解耦锁相环(decoupled double synchronous properties of VSP_PLL adopting different regulators are reference frame PLL，DDSRF_PLL)[9-10]、双二阶通 analyzed, thus an optimization method for the regulator, 用积分器锁相环(double second order generalized including its type and parameters, is obtained. Experimental integrator PLL，DSOGI-PLL)[11]，解决了频率适应 results validate that using