StudyofhighperformanceTSVviafor3Dintegration.doc

Study of high performance TSV via for 3D integration Song Liu*, Guangbao Shan, Hu Zhan Xian microelectronics technology research institute, Xi’an, Shaanxi, china * Email: liusongkaoyan@126.com Abstract 3D integration based on TSV technology is the key solution to the development bottlenecks of conventional 2D IC. As reduction of interconnection path with stacked structure, TSV technology can overcome many 2D IC scaling limits, such as global latency and high power consumption. Despite of numerous advantages, it is still a challenge that how to fabricate high performance TSV via. In this article, it successfully fabricates the small size vias (diameter diameter=5μm, AR10:1, sidewall taper angle 90°±2°) with the good straight profile and smooth sidewall by optimized Bosch process and ICP etcher with pulsating LF bias power, which is suitable for 3D integration. Keywords: 3D integration; TSV; Optimized Bosch process; 1. Introduction The development of integrated circuit has been driven by Moore’s law more than four decades. Owning to shrinking the critical size continuously, the performance and integration density has been increased every year. However, today it has become a challenge. On one hand Moore’s law will encounter the “red brick wall” somewhere in the 32-22nm nodes [1], and on the other the critical size will finally approach the physical limit. Moreover several development bottlenecks has arisen, such as materials selection, high cost of extreme UV lithography and interconnect delay caused by the one-chip wiring, etc. To overcome above problems and increase future IC performance, the ITRS roadmap shows 3D integration as a key technique [2]. TSV is an emerging technology of realizing 3D integration circuit. By vertical interconnects running through the stacks, two or more chips are joined. The TSV stacking connections between chips is micron scale, which is much shorter than that of conventional 2D IC. As a result, the bandwidth can be improved by 2-3 o