用quartusⅡ设计一个四位二进制全减器.docVIP

EDA技术与VHDL作业 作业名称 用quartusⅡ设计一个四位二进制全减器 学生姓名 邹运 班 级 电技122 学 号 2012301030230 任课教师 吴君鹏 完成时间 2014.3.22 用VHDL语言编写如下： library ieee; use ieee.std_logic_1164.all; entity quanjian is port(a,b,c:in std_logic; sout,jout:out std_logic); end; architecture one of quanjian is signal abc:std_logic_vector(2 downto 0); begin abc=abc; process(abc) begin case abc is when000= sout=0;jout=0; when001= sout=1;jout=1; when010= sout=1;jout=1; when011= sout=0;jout=1; when100= sout=1;jout=0; when101= sout=0;jout=0; when110= sout=0;jout=0; when111= sout=1;jout=1; when others=null; end case; end process; end one; library ieee; use ieee.std_logic_1164.all; entity quanjian4 is port(a11,a12,a13,a14,b11,b12,b13,b14:in std_logic; s1,s2,s3,s4,j4:out std_logic); end; architecture two of quanjian4 is signal d,e,f:std_logic; component quanjian port(a,b,c:in std_logic; sout,jout:out std_logic); end component; begin u1:quanjian port map(a=a14,b=b14,c=0,jout=d,sout=s4); u2:quanjian port map(a=a13,b=b13,c=d,jout=e,sout=s3); u3:quanjian port map(a=a12,b=b12,c=e,jout=f,sout=s2); u4:quanjian port map(a=a11,b=b11,c=f,jout=j4,sout=s1); end two; 生成电路图如下： 仿真波形如下：