用verilog写的正弦波发生器资料.docVIP

module sin(clk,rst_n,clock_1,addr_div_1,sin_data); input clk; input rst_n; output[9:0] sin_data; output[9:0] addr_div_1; //output[9:0] addr_div; output clock_1; wire clock; wire[9:0] addr_div; wire[9:0] address; wire[9:0] line; //wire[7:0] q; //wire[9:0] cnt_temp; div U1( .clk(clk), .rst_n(rst_n), .clock_1(clock_1), .clock(clock) ); counter U2( .clock(clock), .rst_n(rst_n), .addr_div_1(addr_div_1), .addr_div(line) ); sinwave U3( .clock(clock), .address(line), .q(sin_data) ); endmodule module div(clk,rst_n,clock,clock_1); input clk; input rst_n; output clock; output clock_1; reg[9:0] count; reg[9:0] count_temp; always@(posedge clk or negedge rst_n) begin if(!rst_n) begin count = 10d0; count_temp=0; end else if(count == 10d24) begin count = 10d0; count_temp = ~count_temp; end else begin count = count + 10d1; end end wire clock,clock_1; assign clock = count_temp; assign clock_1 = count_temp; endmodule module counter(clock,rst_n,addr_div,addr_div_1); input clock; input rst_n; output[9:0] addr_div; output[9:0] addr_div_1; reg[9:0] cnt; reg[9:0] cnt_temp; always@(posedge clock or negedge rst_n) if(!rst_n) cnt = 10d0; else if(cnt == 10d1023) cnt = 10d0; else cnt = cnt + 10d1; always@(posedge clock or negedge rst_n) if(!rst_n) cnt_temp = 10d0; else if(cnt == 10d1023) cnt_temp = 10d0; else cnt_temp = cnt; wire[9:0] addr_div,addr_div_1; assign addr_div = cnt_temp; assign addr_div_1 = cnt_temp; endmodule //正弦波形数据，做ROM用 WIDTH=10; DEPTH=1024; ADDRESS_RADIX=UNS; DATA_RADIX=UNS; CONTENT BEGIN 0 : 511; 1 : 514; 2 : 517; 3 : 520; 4 : 524; 5 : 527; 6 : 530; 7 : 533; 8 : 536; 9 : 539; 10 : 542; 11 : 545; 12 : 549; 13 : 552; 14 : 555; 15 : 558; 16 : 561; 17 : 564; 18