并联再生锁存比较器研究报告.doc

东南大学 模拟实训MPW流片报告 课题名称： 预放大再生比较器 学号： 指导老师： 摘要 比较器是电子系统中应用较为广泛的电路之一。比较器的设计以开环高增益放大器的设计为基础。虽然和运算放大器相比比较器的应用范围相对狭窄但比较器仍在很多应用中不可或缺尤其在模数转换器Analog-to-digital converters，简称 ADC中。比较器作为流水线型ADC的关键模块其速度、功耗等性能对整个模数转换器的速度和功耗都有着至关重要的影响。 在各种比较器结构中预放大再生比较器速度快、功耗低、失调电压小被广泛应用于高速比较器。本文基于预放大再生理论采用 TSMC 3.3V 0.35μm CMOS 工艺设计一种适用于流水线型 ADC 的高速低功耗比较器电路。该比较器由前置放大器比较器和SR锁存电路构成。经过Cadence软件下的Virtuoso平台对电路进行前仿真比较器工作电压为3.3V共模输入电压1.6V在500MHZ的时钟频率下能够实现精度为30uV的比较功耗为5.6mW传输时延为ns，翻转电压0.4mV。 Abstract Comparator is one of the most important units widely used in electronic systems. The design of a comparator is based on loop gain amplifier. Compared with amplifiers, comparators are not that widely used, but it is really necessary especially in Analog-to-digital converters (ADC). The comparator is a crucial part of ADC. Its speed and power have great impact on the characteristic of the whole ADC. Being one of various architectures, preamplifier-latch is widely used as high-speed comparator due to its high-speed, low-power and small offset voltage. Based on preamplifier-latch comparator, adopted TSMC 0.13μm CMOS process, a high-speed, low-power comparator applied for pipelined-ADC is proposed in this paper. This comparator consists of three blocks:pre-amplifier, comparator and SR latch. The pre-simulations use Virtuoso simulation of Cadence, the comparator’s work voltage is 1.8V, and common input voltage is 1.6V, the simulation results indicate that the resolution of the comparator is 30uV, transmission delay is less than 4ns and power dissipation is about 5.6mW under the 500MHZ clock. Key Words: Comparator, Preamplifier-latch, High-speed low-power 目录 摘要 I Abstract II 第一章 绪论 1 1.1 背景 1 1.2 本文的研究内容和结构安排 1 第二章 比较器电路的基本模型 2 2.1 比较器电路的系统参数分析 2 2.1.1 主要性能参数 3 2.1.2 比较器静态分析 5 2.1.3 比较器动态特性 6 2.2 比较器的电路结构与分析模型 7 2.2.1 开环比较器 8 2.2.2 离散时间比较器 9 2.2.3 高速比较器 13 2.3 几种常见的比较器结构 15 2.3.1 电阻分配式比较器 15 2.3.2 差分对比较器 16 2.3.3电荷分配型比较器 16 2.4 小结 17 第三章