大工CMOS数字集成电路总复习.ppt

* Starting at the bottom of the design abstraction chart Gate Oxide – insulator NMOS – since carriers are electrons (n type carriers) M – metal; O – oxide; S – semiconductor Field oxide isolates one device from neighboring devices Base technology for the semester 0.25 micron transistor length L (drawn separation from source to drain) – 0.24 effective 1.0 micron transistor width W for minimum size transistor 2.5V supply voltage VDD 0.43 (-0.4) threshold voltage for NMOS (PMOS) devices so min W/L ratio in max for 250nm technology is 1/.24 View transistor as a switch with an infinite off-resistance and a finite on-resistance * * Inverter – the nucleus of all digital designs; foundation of more intricate gates Design metrics – cost (area); integrity and robustness (static – steady-state behavior); performance (dynamic or transient behavior); energy efficiency * For class handout – hide for class * A good device has a small oxide thickness (-3nm), a small length (-25nm), a higher width (+30nm) and a smaller threshold (-60mV). The opposite is true for a bad device. * VTC characteristics are dependent upon the data input patterns applied to the gate (so the noise margins are also data dependent!) Threshold voltage of M2 will be higher than transistor M1 due to body effect Case 1 – both transistors in the PUN are on simultaneously for A=B=0, representing a strong pull-up. In the other two cases only one of the pull-up devices is on. So the VTC is shifted left as a result of the weaker PUN for the second and third cases. Case 2 – see Case 3, small difference can be attributed to the body effect of M2 and the drive voltage Case 3 – M2 as resistor in series with M1, so only small effect on VTC; since pulldown is strong and pullup weaker than case 1, VTC shifted to the left (also have to discharge both CL (on the output) and Cint (possibly) thru M1 so will also be slower!) * * Assumes inputs of 0 and 1 are equally likely. 只要当输出在上一个求值阶段被放电时，预冲阶段就会发生0－1翻转。 For d