格雷码和二进制的相互转换-vhdl程序研讨.docxVIP

1. B2G_converter 1) Screenshot of iSim simulation results: note: from the beginning point at 1,000ns, input(i5binary) changes every other 50ns a) i5binary input from 0 to 6 i5binary o5graycode Delay of output (ns) 00000 00000 6.691 00001 00001 6.516 00010 00011 6.517 00011 00010 6.516 00100 00110 6.580 00101 00111 6.516 00110 00101 6.517 b) i5binary input from 7 to 13 i5binary o5graycode Delay of output (ns) 00111 00100 6.516 01000 01100 6.197 01001 01101 6.516 01010 01111 6.517 01011 01110 6.516 01100 01010 6.580 01101 01011 6.516 c) i5binary input from 14 to 20 i5binary o5graycode Delay of output (ns) 01110 01001 6.517 01111 01000 6.516 10000 11000 5.210 10001 11001 6.516 10010 11011 6.517 10011 11010 6.516 10100 11110 6.580 d) i5binary input from 21 to 27 i5binary o5graycode Delay of output (ns) 10101 11111 6.516 10110 11101 6.517 10111 11100 6.516 11000 10100 6.197 11001 10101 6.516 11010 10111 6.517 11011 10110 6.516 e) i5binary input from 28 to 31 i5binary o5graycode Delay of output (ns) 11100 10010 6.580 11101 10011 6.516 11110 10001 6.517 11111 10000 6.516 2) VHDL for Binary-to-Gray-Code converter: ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:02:37 09/15/2015 -- Design Name: -- Module Name: b2g_converter - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity b2g_converter is Port ( i5Binary : in STD_LOGIC_VECTOR (4