CH4_逻辑处理与组合逻辑电路.pptVIP

* 邏輯處理與組合邏輯電路 第四章 儒林圖書公司 TB061 VHDL數位電路設計實務教本 使用Quartus II * A=B; --將訊號B傳遞到A A=B after 10ns ; B A 0 5 10 15 20 25 30 35 Input Output Note: = is signal assignment Example-真值表 * ? 輸入 ? 輸出 A B C D 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 0 library IEEE; use IEEE.STD_LOGIC_1164.all; ? entity bol is port ( A,B,C: in STD_LOGIC; D : out STD_LOGIC); end bol; ? architecture a of bol is begin D = ((not A) and B and (not C)) or (A and B and (not C)); end a; * 輸入 輸出 S1 S0 M0 M1 M2 M3