锁相环频率合成器简述及其电路设计-陆顺杰学案.docxVIP

本科生毕业论文（设计） 题 目 锁相环频率合成器简述及其电路设计 学 院 电子信息学院 专 业 电子信息工程 学生姓名 　 陆顺杰 学 号 1142051154 年级 2011 指导教师 华伟　 锁相环频率合成器简述及其电路设计 专业：电子信息工程 学生：陆顺杰 指导老师：华伟 摘要：随着电子技术的发展，各种通信电路对频率源的要求越来越高，锁相环频率合成技术提供了一个可行方案来满足愈发苛刻的通信要求。尤其是随着数字电路快速发展，数字式锁相环频率合成器的性能有了极大的提升，特别是频率分辨率和频率转换时间。本文简要介绍了锁相环的基本工作原理，重点介绍了电荷泵式锁相环频率合成器的各个组成部件及其工作原理，包括鉴频鉴相器（PFD）、电荷泵(CP)、环路滤波器(LPF)、压控振荡器(VCO)和高速可编程分频器，并用AT89S52芯片设计了一个频率控制电路，利用集成压控振荡器的ADF4351芯片作为核心器件，设计了一个从800MHz到2600MHz的宽频带锁相环频率合成电路，经过调试，其测试性能良好，能够满足普通的通信应用需求。 关键词：PLL、频率合成器、ADF4351 The summary of PLL frequency synthesizer and its circuit design Major: Electronics and Information engineering Student: ShunJie Lu Supervisor: Wei Hua Abstract: With the development of electronic technology, the demand of frequency source for kinds of communication circuit is becoming higher and higher. The phase-locked loop frequency synthesis technology provides a feasible scheme to meet the increasingly demanding requirements of communication. Especially with the rapid development of digital circuit, the performance of digital phase locked loop frequency synthesizer has a great improvement, especially including the frequency resolution and frequency conversion time. This paper briefly introduced the basic principle of phase-locked loop, mainly introduced the component parts and working principle of charge pump phase-locked loop frequency synthesizer , including frequency phase detector, charge pump, loop filter, voltage controlled oscillator and high speed programmable frequency divider，and designed a frequency control circuit with AT89S52 chip , used the integrated VCO ADF4351 chip as the core device, designed a wide-band PLL frequency synthesis circuit from 800 MHz to 2600 MHz, after debugging, the test performance is good, and can satisfy the demand of the common communication applications. Key words: PLL、frequency synthesizer、ADF4351 目录 第一章 绪 论 5