EDA部分课件(常见电路).ppt

library ieee; use ieee.std_logic_1164.all; ENTITY and2 IS PORT(a,b:IN BIT; y1:OUT BIT); END and2; ARCHITECTURE beh OF and2 IS BEGIN process(a,b) begin if a=‘1’ and b=‘1’ then y1=‘1’; else y1=‘0’; end if ; end process; end beh; 三态输出门 三态输出门有三种可能的输出状态：高电平、低电平和高阻态。三态输出门简称三态门，主要用于总线结构中。三态门的电路图如图2-5-6所示，有一个输入端A，一个输出端Y和一个控制端EN。当EN= ‘1’时，Y=A；当EN= ‘0’时，Y= ‘Z’。 例 三态门的VHDL程序名称是TSG.VHD，程序描述如下。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY TSG IS PORT ( A, EN : IN STD_LOGIC; Y : OUT STD_LOGIC ); END TSG; ARCHITECTURE STR OF TSG IS BEGIN Y = ‘Z’ WHEN EN=‘1’ ELSE A ; END STR ; 双向总线缓冲器 Library ieee; Use ieee.std_logic_1164.all; Entity tri_bigate is port( a,b:inout std_logic_vector(7 downto 0); en:in std_logic; dr:in std_logic); entity tri_bigate; architecture rt of tri_bigate is signal aout,bout:std_logic_vector(7 downto 0); begin P1:process(a,dr,en) begin if ((en=‘0’) and (dr=‘1’) then bout=a; else bout=“ZZZZZZZZ”; end if; b=bout; end process p1; P2: process(b,dr,en) begin if ((en=‘0’) and (dr=‘0’) then bout=b; else aout=“ZZZZZZZZ”; end if; a=bout; end process p2; end rt; 使用条件赋值语句 architecture behav2 of encoder is begin y=“111” when (input(0)=‘0’) else “110” when (input(1)=‘0’) else “101” when (input(2)=‘0’) else “100” when (input(3)=‘0’) else “011” when (input(4)=‘0’) else “010” when (input(5)=‘0’) else “001” when (input(6)=‘0’) else “000” when (input(7)=‘0’) else “XXX”; end behv2; 使用LOOP语句 architecture behav3 of priorityencoder is begin process( input) variable i:integer; begin for i in 0 to 7 loop if input(i) =‘0’ then y=conv_std_logic_vector(i,3); end if; end loop;