verilog 分器,30s计数器及交通灯控制器设计.docVIP

分频器 module div(clk, div1,div2,div3); input clk; output div1; output div2; output div3; reg [31:0] counter1; reg [31:0] counter2; reg [31:0] counter3; reg div1; reg div2; reg div3; initial begin div1=0;div2=0;div3=0; counter1=0;counter2=0;counter3=0; end always @(posedge clk) begin /*if(counter1==2) counter1 = 0;else counter1 = counter1+1; if(counter2==3) counter2 = 0;else counter2 = counter2+1; if(counter3==4) counter3 = 0;else counter3 = counter3+1;*/ if(counter1= counter1 = 0;else counter1 = counter1+1; if(counter2==24999) counter2 = 0;else counter2 = counter2+1; if(counter3= counter3 =0;else counter3 = counter3+1; end always @(posedge clk) begin /*if(counter1==2) div1 = ~div1; if(counter2==3) div2 = ~div2; if(counter3==4) div3 = ~div3;*/ if(counter1= div1 = ~div1; if(counter2==24999) div2 = ~div2; if(counter3= div3 = ~div3; end endmodule 30s计数器 module count30(div1,number,direction ); input div1; output [4:0] number; output direction; reg [4:0] number; reg direction; initial begin direction=0; number=30; end always@(posedge div1) begin if(number==0) begin direction=~direction; number=30; end else number=number-1; end endmodule 控制器 module moniter( div3, number, direction, eastred, eastyellow, eastgreen, northred, northyellow, northgreen ); input div3; input direction; input [4:0]number; output eastred; output eastyellow; output eastgreen; output northred; output northyellow; output northgreen ; //wire [4:0] number; //reg direction; reg eastred; reg eastyellow; reg eastgreen; reg northred; reg northyellow; reg northgreen ; initial begin eastred=1; eastgreen=0;