Counter_8计数器.docVIP

源代码清单： module jishuqi8 out,cout,clk,load,data ; output [2:0] out; output cout; input load,clk; input [2:0] data; wire [2:0] data; wire load; reg [2:0] out; reg cout; wire clk; always @ posedge clk out out+1; always @ out or load begin if load out data; if out 3d7 cout 1b1; else cout 0; end endmodule 激励模块: module stimulus; wire [2:0] OUT; wire COUT; reg [2:0] DATA; reg CLK,LOAD; jishuqi8 test OUT,COUT,CLK,LOAD,DATA ; initial begin CLK 0;LOAD 0;DATA 3b000; end always #5 CLK ~CLK; initial begin $monitor $time,OUT %b,COUT %b,DATA %b,LOAD %b,OUT,COUT,DATA,LOAD ; #10 LOAD 1; #4 LOAD 0; #120 LOAD