用verilog hdl实现任意八位序列检测.docVIP

/* 用verilog hdl实现任意八位序列检测，clk是时钟信号，fin串行输入序列，i_check是输入要检测的序列，o_ckeck是输出要检测的序列，因为在实验版已经要数码管译码器，所有直接输出，输入正确的序列显示为F，错误则为5 */ module scheck(clk,fin,rst,i_check,o_check,sout); input clk; input fin; input rst; input [7:0] i_check; output [7:0] o_check; output [3:0] sout; reg [2:0] st; reg [3:0] rsout; reg rpin; always @ (posedge clk or posedge rst) begin if(rst) begin rpin=0; end else rpin=fin; end wire pin; assign pin=rpin; always @(posedge clk or posedge rst) begin if(rst) begin st=0; rsout=4d5; end else begin case(st) 3d0,3d1,3d2,3d3,3d4,3d5,3d6,: if(pin==i_check[7-st]) st=st+1b1; else st=0; 3d7:if(pin==i_check[0]) begin rsout=4d15; st=0; end else begin rsout=4d5; st=0; end default:begin st=0; rsout=4d5; end endcase end end assign o_check=i_check; assign sout=rsout; endmodule