Dual gate flow.ppt

Dual-gate polycide process Flow * N well N well L05 – To define Nwell (PMOS) Nwell implant : P+1.30E13/cm2, 490KeV, 0 tilt Punch through prevention implant : P+5.00E12/cm2, 180KeV, 7 tilt Vt adjust implant : BF2+5.30E12/cm2, 080KeV, 7 tilt Post Dielectric PRS – Plasma resist strip Polymer removal : SPM 20/10 Nwell implant Vt adjust implant Punch through implant Resist Resist 5V for I/O 3.3V for internal circuit N well N well P well L15 Mask - to define P field (NMOS) Vt adjust implant BF2+1.50E12/cm2,080KeV, 7 tilt Punch through prevention implant : B+5.00E12/cm2, 070KeV, 7 tilt P field implant (p well) B+1.00E13/cm2, 180KeV, 7 tilt Resist Resist P well Vt adjust implant PField implant Punch through implant 5V for I/O 3.3V for internal circuit N well N well P well Post Dielectric PRS--plasma resist strip SPM 10 SPM--QDR--FR--SRD In this case, SC1 is not included since there will be a RCA cleaning step before gate oxide growth Oxide removal--300 The sacrificial oxide is removed by DHF 10:1 P well 5V for I/O 3.3V for internal circuit N well N well P well Gate1 oxide = 90A RCA--to clean the wafer before pad oxide growth to ensure the quality of the gate oxide, the DHF in this RCA step is longer Gate oxide growth 90A Gate oxide growth by sub-wet oxidation. In subwet oxidation, the oxygen gas flow is only half of the hydrogen P well 5V for I/O 3.3V for internal circuit Resist Resist N well P well N well P well L61 (N-thin gate) VTN Implant BF2+8.00E11/cm2, 30KeV, 7 tilt NTHRU Implant B+1.00E12/cm2, 50KeV, 7 tilt SPM 20 5V for I/O 3.3V for internal circuit Resist N well P well N well P well L38 (Dual gate) Thin VTN Implant BF2+1.50E12/cm2, 30KeV, 7 tilt 5V for I/O 3.3V for internal circuit Resist N well P well N well P well Oxide Removal BOE – For oxide removal with resist present, BOE is used due to: BOE has higher PH than DHF, and will not attack resist as much as DHF Oxide removal rate is uniform SPM – 20 RCA – T