General DI Backend Flow And Tape-out Reivew 20110527.ppt

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Company Proprietary and Confidential DRC Debug Library related Latch-up error, pin off-grid error, macro surrounding error, error waived in release notes, etc. Techfile related Metal spacing error, via array spacing error, etc. EDA tool and flow related Fat metal spacing error, metal hole error, metal edge error, metal density, etc. Special rule related Well antenna error, etc. Runset options related Metal stack, package type, DFM rule, etc. Company Proprietary and Confidential Antenna Debug Library related Library antenna info missing Digital core with flatten antenna file Techfile related Antenna checking mode Diode calculating mode EDA tool and flow related Precision different between EDA and library antenna file like 0.001 and 0.0001 Antenna Techfile Sample Company Proprietary and Confidential Company Proprietary and Confidential LVS Debug Intrinsical Factors Layout vs Source One on one for each element Ports Data/control signal, local PG, global PG Nets Hierarchical nets, global nets Instances Std cell, memory, IO, IP, transistor device Property MOS, Resistor, Capacitor, Diode, Qpnp/npn Options Setting LVS Runset Design Options LVS Runset Tool Options Spice Bipolar Options Company Proprietary and Confidential Typical LVS Errors Layout errors Stream in with wrong reference cell from different library Old version library, wrong library Stream in with wrong reference via generation from different PR techfile Old PR library with old techfile Source errors Sub cell different definition in different cdl Same subckt occurs in different sub macro cdl Wrong sub cell instance number Power/ground or split IO added by manual Case sensitive issue Company Proprietary and Confidential LVS Runset Options Sample Design Options Tool Options Spice Bipolar Options Sample Company Proprietary and Confidential Company Proprietary and