简易数字频率计设计论文（cpld+vhdl) 本科毕业论文.docVIP

摘要 采用自上向下的设计方法,设计了基于复杂可编程逻辑器件的数字频率计以AT89C51单片机作为系统的主控部件完成电路的测试信号控制、数据运算处理、键盘扫描和控制数码管显示用VHDL语言编程由CPLD(Complex Programmable Logic Device)完成各种时序控制及计数功能该系统具有结构紧凑、可靠性高、测频范围宽和精度高等特点? 关键词 可编程逻辑器件? Abstact With the adoption of the top-down design method and AT89C51 SCMC (Single Chip Mico Computer) as the master control component of the system,the circuit test signalcontrolling,data operation processing,keyboard scanning,and nixie tube display as well were completed by the digital cymometer.A CPLD programmed by VHDL,realized various sequence control and