fir16xin程序.docVIP

1.寄存器 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY jicunqi IS PORT (rst,clk: IN STD_LOGIC; d:IN STD_LOGIC_VECTOR (9 DOWNTO 0); q:OUT STD_LOGIC_VECTOR (9 DOWNTO 0)); END jicunqi; ARCHITECTURE dff16 OF jicunqi IS BEGIN PROCESS (rst,clk) BEGIN IF(rst=1)THEN q=(OTHERS=0); ELSIF(clkEVENT AND clk=1)THEN q=d; END IF; END PROCESS; END dff16; 2.加法器 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY add101011 IS PORT(a,b: IN SIGNED(9 DOWNTO 0); clk: IN STD_LOGIC; s:OUT