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OpenMP-based parallelization on an MPCore multiprocessor platform – A performance and power analysis??Original Research ArticleJournal of Systems Architecture, Volume 54, Issue 11, November 2008, Pages 1019-1029H. Blume, J. von Livonius, L. Rotenberg, T.G. Noll, H. Bothe, J. Brakensiek ?Close preview??|?? Purchase PDF (739 K) ??|?? Related articles??|??Related reference work articles???? AbstractAbstract | Figures/TablesFigures/Tables | ReferencesReferences Abstract In this contribution, the potential of parallelized software that implements algorithms of digital signal processing on a multicore processor platform is analyzed. For this purpose various digital signal processing tasks have been implemented on a prototyping platform i.e. an ARM MPCore featuring four ARM11 processor cores. In order to analyze the effect of parallelization on the resulting performance-power ratio, influencing parameters like e.g. the number of issued program threads have been studied. For parallelization issues the OpenMP programming model has been used which can be efficiently applied on C-level. In order to elaborate power efficient code also a functional and instruction level power model of the MPCore has been derived which features a high estimation accuracy. Using this power model and exploiting the capabilities of OpenMP a variety of exemplary tasks could be efficiently parallelized. The general efficiency potential of parallelization for multiprocessor architectures can be assembled. Article Outline 1. Introduction 2. MPCore architecture 3. Parallelization of programs using OpenMP 4. Exemplary parallelization of a motion estimation algorithm 5. Hybrid FLPA/ILPA modeling of the MPCore 6. Evaluation of the MPCore architecture executing parallelized tasks 7. Conclusion References Vitae Issues in the development of a practical NoC: the Proteo concept??Original Research ArticleIntegration, the VLSI Journal, Volume 38, Issue 1, October 2004, Pages 95-105David Sigüenza-Tortosa, Tap