4位并行比较器verilog.docVIP

比较模块： module compare4 a_gt_b, a_eq_b, a_it_b, in1, in2 ; input [3:0] in1, in2; output a_gt_b, a_eq_b, a_it_b; reg a_gt_b, a_eq_b, a_it_b; always @ in1 or in2 begin if in1 in2 a_eq_b 1; else a_eq_b 0; if in1 in2 a_gt_b 1; else a_gt_b 0; if in1 in2 a_it_b 1; else a_it_b 0; end endmodule 测试模块： module test; reg [3:0] a, b; wire a_gt_b, a_eq_b, a_it_b; compare4 mycom .a_gt_b a_gt_b , .a_eq_b a_eq_b , .a_it_b a_it_b , .in1 a , .in2 b ; initial begin #5 a 4b0010; b 4b0111; #15 a 4b0011; b 4b0101; #20 a 4b1010; b 4b0011; #30 a 4b0010; b 4b0010; end endmodule 测试波形：