Preface-海南大学HainanUniversity.pptVIP

Sequential Logic Design Principles Sequential Logic Design Principles Sequential Logic Design Principles Sequential Logic Design Principles Specialized Words Exercises * * 7.1 Bistable Elements 7.2 Latches and Flip-Flops 7.4 Clocked Synchronous State-Machine Analysis 7.5 Clocked Synchronous State-Machine Design Return Introduction 7.3 Clocked Synchronous State-Machine Structure A sequential logic circuit is one whose outputs depend not only on its current inputs, but also on the past sequence of inputs, possibly arbitrarily far back in time. Combinational circuit Memory circuit Z1 Zj Y1 Yr ... ... X1 Xi Q1 Qr ... ... output equation drive equation state equation Z=F1（X，Qn） Y=F2（X，Qn） Qn+1=F3（Y，Qn） Next Return Finite-state machine: In a digital logic circuit, state variables are binary values. A circuit with n binary state variables has 2n possible states which is always finite, so sequential circuits are sometimes called finite-state machines. State: The state of a sequential circuit is a collection of state variables whose values at any one time contain all the information about the past necessary to account for the circuit’s future behavior. Next Back Duty cycle: The duty cycle is the percentage of time that the clock signal is at its asserted level. The state changes of most sequential circuits occur at times specified by a free-running clock signal. tH tL tper Period=tper Frequency=1/tper Duty cycle=tH/tper Return FF=Flip-Flop 触发器 CLK=Clock 时钟 Clocked Synchronous State-Machine 同步时序状态机（同步时序逻辑电路） duty cycle 占空比 stable 稳态 metastable 亚稳态 latch 锁存器 master-slave 主从 positive-edge-triggered 上升沿触发 negative-edge-triggered 下降沿触发 Return P647~651 7.9, 7.15, 7.16, 7.17, 7.18, 7.19, 7.30, 7.32, 7.7.34, 7.35 Return *