verilog自动手动换挡频率计.docxVIP

直接上源码，不解释，自己建工程运行即可看到功能！module control(cp1024hz,started,reset,k1,k2,k3,k4,k5,k6,zero1,zero2,zero3,zero4,zero5,zero6,time_out,mode,flag_pressed,sound_en,latch_en);//yesdinput cp1024hz,started,reset;input k1,k2,k3,k4,k5,k6;//抢答的6个按键，由cp1024hz扫描是否有按键input zero1,zero2,zero3,zero4,zero5,zero6;//6个用?的分数是否为0，并将分数为0的淘汰input time_out;//倒计时已完output flag_pressed,sound_en,latch_en,mode;//是否已按键;声音控制;模式控制;输出模式regflag_pressed,sound_en,latch_en;reg[3:0] mode;always @(posedge cp1024hz)beginif(!started)//当started=0时，对系统进行初始化，同时将mode置0；beginmode=0;flag_pressed=1;//利用设置这个将k1~k6屏蔽sound_en=0;latch_en=0;endelsebeginif(reset)//started=1已开始，reset=1新一轮抢答beginflag_pressed=0;sound_en=0;latch_en=0;mode=7; //mode置为抢答模式endelsebeginif(time_out)beginsound_en=1;//时间完了之后，响声提示endelsebeginif(!flag_pressed k1 !zero1)//当started=1时，按下key1beginflag_pressed=1;sound_en=1;latch_en=1;//按键之后，产生相应电平mode=1;endelse if(started !flag_pressed k2 !zero2)beginflag_pressed=1;sound_en=1;latch_en=1;//按键之后，产生相应电平mode=2;endelse if(!flag_pressed k3 !zero3)beginflag_pressed=1;sound_en=1;latch_en=1;//按键之后，产生相应电平mode=3;endelse if(!flag_pressed k4 !zero4)beginflag_pressed=1;sound_en=1;latch_en=1;//按键之后，产生相应电平mode=4;endelse if(!flag_pressed k5 !zero5)beginflag_pressed=1;sound_en=1;latch_en=1;//按键之后，产生相应电平mode=5;endelse if(!flag_pressed k6 !zero6)beginflag_pressed=1;sound_en=1;latch_en=1;//按键之后，产生相应电平mode=6;endendendendendendmodulemodule display(cp1024hz,mode,setted_score,score1,score2,score3,score4,score5,score6,time_countdown,disp);//yesdinput cp1024hz;input[3:0] mode,time_countdown;//从time_count引出input[7:0] setted_score,score1,score2,score3,score4,score5,score6;outputdisp;reg [3:0]mode_disp;reg[7:0] disp;always @(posedge cp1024hz)begincase(mode)4b0000 :disp=setted_score;4b0001 :disp=score1;4b0010 :disp=score2;4b0011 :disp=score3;4b0100 :disp=score4;4b0101 :disp=score5;4b0110 :disp=score6;4b0111 :begindisp[3:0]=time_countdown;disp[7:4]=0;enddefault :disp=setted_score;endcaseendendmodulemodule mode_latch_change(cp10