ClockNoiseinSampledDataSystems.pptVIP

Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems Clock Noise in Sampled Data Systems If two signal lines run side by side they interact in two ways – changing voltages on one line couple capacitively to the other, and changing currents in one line couple inductively to the other. With short runs of normal logic the noise immunity of logic gates allows us to disregard these effects, but with long runs, or when one of the signals is a sampling clock and liable to be phase modulated by noise, we must take steps to prevent them. The simplest solution is to run a ground return conductor between each signal conductor. These act as electrostatic (Faraday) shields to capacitive coupling and also, by causing each signal/return pair to act as a transmission line, minimise magnetic coupling. An even better solution for sampling clock signals is to route them well away from any other digital signals. The best way to eliminate jitter caused by common-mode noise between the analog and digital grounds is to build the sampling clock generator on the system analog ground. This gives rise to jitter on the signal going to the DSP, but, as we have seen, this rarely matters. Unfortunately many IC crystal oscillators use one or more logic gates with a feedback resistor for bias. This arrangement is adequate for many applications, but it has worse phase noise and ageing than a purpose-designed oscil