用VHDL语言设计BCD-七段译码.docVIP

简单电路的VHDL语言描述 一、实验内容 1.用VHDL语言设计BCD-七段译码驱动芯片，编译、下载，并进行电路功能验证。 (1) 程序源代码 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DELED IS PORT(NUM:IN STD_LOGIC_VECTOR(3 DOWNTO 0); A,B,C,D,E,F,G: OUT STD_LOGIC); END ENTITY DELED; ARCHITECTURE ART OF DELED IS SIGNAL LED:STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN PROCESS(NUM) BEGIN CASE NUM IS WHEN 0000=LED=1111110; WHEN 0001=LED=0110000; WHEN 0010=LED=1101101; WHEN 0011=LED=1111001; WHEN 0100=LED=0110011; WHEN 0101=LED=10110