再来看课程主要内容讲义.ppt

* 假定Cache的容量为2N为字节（例中N=10），主存块大小为32字节，主存的容量为232字节。那么，32位主存地址的划分应该如下：低5位表示块内字节号，中间5位表示Cache的行（槽）号，高12位表示主存标志。 * Data cache uses 1 byte as the smallest unit but instruction cache uses 1 word as the smallest units This is yet another example showing that the byte select is divided into block offset and byte offset. Different computer systems have different designing choice. Designing shown in this example is good for both Instruction cache and data cache. * 访存过程： CPU给出一个20位主存地址，根据高11位的内容同时与Cache中各槽的标志位进行比较。 若能找到相等的槽，则说明要访问的单元在该槽中。再根据后9位字号找到相应的字取到CPU中。 若全都不相等，则说明要访问的单元不在Cache中。 * 访存过程： CPU给出一个20位主存地址，根据中间3位的内容找到对应的Cache组，再将前8位同时与该组中各槽的标志位进行比较。 若能找到相等的槽，则说明要访问的单元在该槽中。再根据后9位字号找到相应的字取到CPU中。 若全都不相等，则说明要访问的单元不在该组中。 * A HIT is when the data the processor wants to access is found in the upper level (Blk X). The fraction of the memory access that are HIT is defined as HIT rate. HIT Time is the time to access the Upper Level where the data is found (X). It consists of: (a) Time to access this level. (b) AND the time to determine if this is a Hit or Miss. If the data the processor wants cannot be found in the Upper level. Then we have a miss and we need to retrieve the data (Blk Y) from the lower level. By definition (definition of Hit: Fraction), the miss rate is just 1 minus the hit rate. This miss penalty also consists of two parts: (a) The time it takes to replace a block (Blk Y to BlkX) in the upper level. (b) And then the time it takes to deliver this new block to the processor. It is very important that your Hit Time to be much much smaller than your miss penalty. Otherwise, there will be no reason to build a memory hierarchy. +2 = 14 min. (X:54) 举例 第0组 第1组 第2组 第3组 第4组 …… …… 第15组 第0 行 第1 行 第2 行 第3 行 0/64/48 1/65/49 2/66/50 3/67/51 4 …… …… 15 16/0/64 17/1/65 18/2/66 19/3/67 20 …… …… 31 32/16 33/17 34/18 35/19 36 …… …… 47 48/32 49/33 50/34 51/35 52 …… …… 63 LRU算法：第一次循环,每一块的第一字未命中,其余都命中; 以后9次循环,有20块的第一字未命中,其余全部命中. 所以,命中率p为 (