ISE各个步骤说明.docVIP

XST Design Flow Overview The following figure shows the flow of files through the XST software. XST Input and Output Files XST supports extensive VHDL and Verilog subsets from the following standards: VHDL: IEEE 1076-1987, IEEE 1076-1993, including IEEE standard and Synopsys? Verilog: IEEE 1364-1995, IEEE 1364-2001 In addition to a VHDL or Verilog design description, XST can also accept the following files as input: XCF Xilinx constraints file in which you can specify synthesis, timing, and specific implementation constraints that can be propagated to the NGC file. Core files These files can be in either NGC or EDIF format. XST does not modify cores. It uses them to inform area and timing optimization surrounding the cores. Note?Cores are supported for FPGAs only, not CPLDs. In addition to NGC files, XST also generates the following files as output: Synthesis Report This report contains the results from the synthesis run, including area and timing estimation. For details, see Viewing a Synthesis Report. RTL schematic This is a schematic representation of the pre-optimized design shown at the Register Transfer Level (RTL). This representation is in terms of generic symbols, such as adders, multipliers, counters, AND gates, and OR gates, and is generated after the HDL synthesis phase of the synthesis process. Viewing this schematic may help you discover design issues early in the design process. For details, see Viewing an RTL Schematic - XST. Technology schematic This is a schematic representation of an NGC file shown in terms of logic elements optimized to the target architecture or technology, for example, in terms of LUTs, carry logic, I/O buffers, and other technology-specific components. It is generated after the optimization and technology targeting phase of the synthesis process. Viewing this schematic allows you to see a technology-level representation of your HDL optimized for a specific Xilinx architecture, which may help you discover design issues early