VHDL数字电路程实验报告.docVIP

VHDL数字电路课程实验报告 实验一 8分频器 一、实验要求：分别用信号量和变量实现八分频器 二、实验过程： 1、代码： 8分频器vhd library ieee; use ieee.std_logic_1164.all; entity freq_divider is port(clk: in std_logic; out1, out2: buffer bit); end freq_divider; architecture example of freq_divider is signal count1: integer range 0 to 7; begin process(clk) variable count2: integer range 0 to 7; begin if(clkevent and clk=1) then count1=count1+1; count2:=count2+1; if(count1=3) then out1=not out1; count1=0; end if; if(count2=4) then out2=not out2; count2:=0; end if; end if; end process; end example; 八分频器tb LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY fd_tb is END fd_tb; architecture behavior of fd_tb is component freq_divider port(clk:IN STD_LOGIC; out1, out2: buffer bit); end component; signal clk:std_logic; signal out1,out2:bit; begin u1: freq_divider port map(clk,out1,out2); process begin clk=0; wait for 50 ns; loop clk=not clk; wait for 25 ns; end loop; end process; end behavior; 2、结果图： 实验二 实现例8.6 实验要求： 电路只有一个输入时钟信号，输出信号在适中的两个边沿都会发生变化 实验内容： 代码 信号发生器vhd ENTITY signal_gen IS PORT (clk: IN BIT; outp: OUT BIT); END signal_gen; ARCHITECTURE fsm OF signal_gen IS TYPE state IS (one, two, three); SIGNAL pr_state1, nx_state1: state; SIGNAL pr_state2, nx_state2: state; SIGNAL out1, out2: BIT; BEGIN PROCESS(clk) BEGIN IF (clkEVENT AND clk = 1) THEN pr_state1 = nx_state1; END IF; END PROCESS; PROCESS (clk) BEGIN IF (clkEVENT AND clk = 0) THEN pr_state2 = nx_state2; END IF; END PROCESS; PROCESS (pr_state1) BEGIN CASE pr_state1 IS WHEN one = out1 = 0; nx_state1 = two; WHEN two = out1 = 1; nx_state1 = three; WHEN three = out1 = 1; nx_state1 = one; END CASE; END PROCESS; PROCESS (pr_state2) BEGIN CASE pr_state2 IS WHEN one = out2 = 1; nx_state2 = two; WHEN two = out2 =