Verilog HDL及Modelsim仿真 范益波.pptVIP

module comcase(a, b, c, d, e); input a, b, c, d; output e; reg e; always @(a or b or c or d) case ({a,b}) 2’b11: e=d; 2’b10: e=~c; 2’b01: e=1’b0; 2’b00: e=1’b1; endcase endmodule case条件语句 module compif(a, b, c, d, e); input a, b, c, d; output e; reg e; always @(a or b or c or d) if(ab) e=d; else if (a~b) e=~c; else if (~ ab) e=1’b0; else if (~a~b) e=1’b1; endmodule if条件语句 module inccase(a, b, c, d, e); input a, b, c, d; output e; reg e; always @(a or b or c ord) case ({a,b}) 2’b11: e=d;