半加器和全加器的設计.docVIP

实验一.半加器，全加器的设计 1，半加器的设计， 方法一 library ieee ; use ieee.std_logic_1164.all; entity h_adder1 is port(a,b :in std_logic; c,s :out std_logic); end entity h_adder1; architecture one of h_adder1 is begin s=a xor b;c=a and b; end architecture one; 运行结果： 方法二： 运行结果： 2，全加器的设计 方法一： library ieee; use ieee.std_logic_1164.all; entity f_adder1 is port(a,b,cin :in std_logic; sum,cout :out std_logic); end entity f_adder1; architecture arch of f_adder1 is component h_adder1 port( a,b :in std_logic; s,c :out std_logic); end component; component or23 port (a,b :in std_logic; c: out std_logic); end component; signal x:std_logic_vector(0 to 2); begin u1: h_adder1 port map(a,b,x(1),x(0)); u2: h_adder1 port map(x(1),cin,sum,x(2)); u3: or23 port map(a=x(0),b=x(2),c=cout); end arch; 运行结果： 方法二： 运行结果： 实验二.四选一数据选择器的设计 1用case语句： library ieee; use ieee.std_logic_1164.all; entity mux4_1a is port(A,B,C,D :in std_logic_vector(3 downto 0); sel :in std_logic_vector(1 downto 0); q :out std_logic_vector(3 downto 0) ); end mux4_1a; architecture arch of mux4_1a is begin process(A,B,C,D,sel) begin case sel is when 00= q=A; when 01= q=B; when 10= q=C; when 11= q=D; when others= null; end case; end process; end arch; 运行结果： 2，用if语句设计： library ieee; use ieee.std_logic_1164.all; entity mux4_1b is port(A,B,C,D :in std_logic_vector(3 downto 0); sel :in std_logic_vector(1 downto 0); q :out std_logic_vector(3 downto 0) ); end mux4_1b; architecture arch of mux4_1b is begin process(A,B,C,D,sel) begin IF sel =00 then q=A; elsif sel = 01 then q=B; elsif sel = 10 then q=C; elsif sel = 11 then q=D; end if end process; end arch; 用with语句设计： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mux4_1c is port(A,B,C,D :in std_logic_vector(3 downto 0); sel :in std_logic_vector(1 downto 0); q :out std_logic_vector(3 downto 0) ); end mux4_1c; architecture arch of mux4_1c is begin with sel select