基于fpga的四選一数据选择器和一位全加器的设计.docVIP

ENTITY mux21 IS PORT(A,B,S : IN BIT; Y : OUT BIT); END ENTITY mux21; ARCHITECTURE one OF mux21 IS BEGIN Y = A WHEN S= 0 ELSE B; END ARCHITECTURE one; ENTITY xor2 IS port(a,b : in bit; c : out BIT); end entity xor2; ARCHITECTURE one OF xor2 IS begin c = 0 when a=b else 1 ; end ARCHITECTURE one; ENTITY mux41 IS PORT(A,B,C,D,S1,S2 : IN BIT; Y : OUT BIT); END ENTITY mux41; ARCHITECTURE ons OF mux41 IS COMPONENT mux21 PORT(A,B,S : IN BIT; Y : OUT BIT); END COMPONENT; COMPONENT xor2 port(a,b : in bit; c : out bit); END COMPONENT; SIGNAL d1,e,f : bit ; BEGIN u1 : mux21 PORT MAP(A=A,B=B,S=S1,Y=e); u2 : mux21 PORT MAP(A=C,B=D,S=S2,Y=f); u3 : xor2 PORT MAP(a=S1,b=S2,c=d1); u4 : mux21 PORT MAP(A=e,B=f,S=d1,Y=Y); END ARCHITECTURE ons; （四选一） LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder IS PORT(A,B : IN STD_LOGIC; CO,SO : OUT STD_LOGIC); END ENTITY h_adder; ARCHITECTURE fh1 OF h_adder IS BEGIN SO = NOT(A XOR (NOT B));CO = A AND B; END ARCHITECTURE fh1; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2a IS PORT(a,b : IN STD_LOGIC; c : OUT STD_LOGIC); END ENTITY or2a; ARCHITECTURE one OF or2a IS BEGIN c = a OR b; END ARCHITECTURE one; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_adder IS PORT(ain,bin,cin : IN STD_LOGIC; cout,sum : OUT STD_LOGIC); END ENTITY f_adder; ARCHITECTURE fd1 OF f_adder IS COMPONENT h_adder PORT(A,B : IN STD_LOGIC; CO,SO : OUT STD_LOGIC); END COMPONENT; COMPONENT or2a PORT(a,b : IN STD_LOGIC; c : OUT STD_LOGIC); END COMPONENT; SIGNAL d,e,f : STD_LOGIC; BEGIN u1 : h_adder PORT MAP(A=ain, B=bin, CO=d, SO=e); u2 : h_adder PORT MAP(A=e, B=cin, CO=f, SO=sum); u3 : or2a PORT MAP(a=d, b=f, c=cout); END ARCHITECTURE fd1; LIBRARY IEEE; （一位全加器）