基于VHDL語言的数字钟设计.docVIP

PAGE PAGE 5 一．程序代码及其仿真： cnt60子模块代码： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY V_cnt60 IS PORT ( clk :IN std_logic; Q0,Q1,Q2,Q3,Q4,Q5,Q6,QC :OUT std_logic); END V_cnt60; ARCHITECTURE func OF V_cnt60 IS SIGNAL count1 :std_logic_vector(3 downto 0); SIGNAL count2 :std_logic_vector(3 downto 0); SIGNAL carryin:std_logic; BEGIN Q0 = count1(0); Q1 = count1(1); Q2 = count1(2); Q3 = count1(3); Q4 = count2(0); Q5 = count2(1); Q6 = count2(2); QC = carryin; process(clk) BEGIN if (clkevent AND cl