Lec17.pptVIP

Jin. UESTC Digital Logic Design and ApplicationJin YanhuaLecture #17 Parity Circuits Adder Last Time DeMultiplexers —— using binary decoders, enable input ? data line Parity Circuits Detect the number of 1 —— Exclusive-OR Data bits + check bit (parity bit) Comparators 1-bit n-bit Last Time Expanding comparators in series 8-bit comparator 74x682 Expanding comparators in Parallel 5.10 Adder 5.10 Adder 5.10 Adder 2. Ripple Adder 3. Iterative Circuit（迭代电路） 4. Carry-Lookahead Adders 4. Carry-Lookahead Adders 74x283 4-bit adder Uses carry lookahead internally 5. Multipliers 6. MSI Arithmetic and Logic Units Chapter 4 Principles Chapter 6 Practices Useful MSI Combinational Logic Device Decoders, Encoders, Multiplexers, Parity Circuits, Comparators, Adders, Three-State Devices Basic function, Cascading, Application 综合应用：利用基本MSI器件作为基本单元设计更复杂的组合逻辑电路 Documentation Standard and Circuit Timing * Digital Logic Design and Application UESTC, Spring 2012 A=B：A⊙B AB：A·B’ AB：A’·B expand in parallel and series 热门促销智能手机推荐/ 4-bit comparator 74x85 ALTBIN AEQBIN AGTBIN Cascading inputs Low-order AGTBOUT = (AB) + (A=B) · AGTBIN ALTBOUT = (AB) + (A=B) · ALTBIN AEQBOUT = (A=B) · AEQBIN If no low-order inputs ALTBIN ? Low-level AEQBIN ? High-level AGTBIN ? Low-level XD[11:0] YD[11:0] [3:0] [7:4] [11:8] XY X=Y XY +5V ABI A=BI ABI ABO A=BO ABO A0~A3 B0~B3 74x85 ABI A=BI ABI ABO A=BO ABO A0~A3 B0~B3 74x85 ABI A=BI ABI ABO A=BO ABO A0~A3 B0~B3 74x85 Build a 12-bit comparators using 74x85s Low-order High-order P0 P1 P2 P3 P4 P5 P6 P7 Logic diagram P463 Figure 6-82 Q1: How to get the following outputs? active-high: P DIFF Q active-high: P EQ Q active-high: P GE Q GE LT Q2: How to expand? Have no cascading inputs! active-high: P LE Q active-high: P LT Q P463 Figure 6-81 24-bit comparators using 74x682s P0~P7 P=Q Q0~Q7 PQ P0~P7 P=Q Q0~Q7 PQ P0~P7 P=Q Q0~Q7 PQ [7:0] [15:8] [23:16] P[23:0] Q[23:0] PEQQ PGTQ 1. Half Adder and