Logic Synthesis.pptVIP

Logic Synthesis Equivalence Checking Application of EC in mP Designs Application of EC in ASIC Designs Basic Model Finite State Machines Finite State Machines Equivalence General Approach to EC Proving R Soundness and Completeness With a candidate for R we can: prove equivalance that means the method is “sound” we will not produce “false positives” but not disprove it: that means the method is “incomplete” we may produce “false negatives” How Do We Obtain R? Reachability analysis: state traversal until no more states can be explored forward backward explicit symbolic Relying on the des