第4章_VHDL结构.ppt

* ARCHITECTURE count_64k OF counter IS BEGIN PROCESS (CLK) VARIABLE count : integer:=0; BEGIN if clear=‘1’ then count:=0; elsif load=‘1’ then count:=data_in; elsif (clk’event) and (clk=‘1’) and (clk’last_value=0) then if (count=65535) then count:=0; else count:=count+1; end if; end if; count_out=count; end PROCESS; End count_65535; --用以上两个构造体分别构建计数器 configuration small_count of counter is for count_255 end for; end small_count; configuration big_count of counter is for count_64k en