实时信号处理作业..docVIP

2 FIR滤波器设计 6 2.1. 原理 6 2.2. 建模 7 2.3. 仿真测试 9 3.3. 建模和求解 11FIR滤波器设计 原理 建模 ===============================查找表================================ LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; ENTITY case3 IS PORT ( table_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0); table_out : OUT INTEGER RANGE 0 TO 6); END case3; ARCHITECTURE LCs OF case3 IS BEGIN -- This is the DA CASE table for -- the 3 coefficients: 2, 3, 1 -- automatically generated with dagen.exe -- DO NOT EDIT! PROCESS (table_in) BEGIN CASE table_in IS WHEN 000 = table_out = 0; WHEN 001 = table_out = 2; WHEN 010 = table_out = 3; WHEN 011 = table_out = 5; WHEN 100 = table_out = 1; WHEN 101 = table_out = 3; WHEN 110 = table_out = 4; WHEN 111 = table_out = 6; WHEN OTHERS = table_out = 0; END CASE; END PROCESS; END LCs; ========================DA_FIR设计================================ LIBRARY ieee; -- Using predefined packages USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; PACKAGE da_package IS -- User defined component COMPONENT case3 PORT ( table_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0); table_out : OUT INTEGER RANGE 0 TO 6); END COMPONENT; END da_package; LIBRARY work; USE work.da_package.ALL; LIBRARY ieee; -- Using predefined packages USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; ENTITY dafsm IS ------ Interface PORT (clk : IN STD_LOGIC; x_in0, x_in1, x_in2 :IN STD_LOGIC_VECTOR(2 DOWNTO 0); y : OUT INTEGER RANGE 0 TO 63); END dafsm; ARCHITECTURE flex OF dafsm IS TYPE STATE_TYPE IS (s0, s1); SIGNAL state : STATE_TYPE; SIGNAL x0, x1, x2, table_in: STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL table_out : INTEGER RANGE 0 TO 7; BEGIN table_in(0) = x0(0); table_in(1) = x1(0); table_in(2) = x2(0); PROCESS------ DA