SoC设计第4章.ppt

SystemC——通道 bool reset( ) {. . .} inline unsigned int start_address ( ) const {. . .} inline unsigned int end_address ( ) const {. . .} private: T* mem; unsigned int m_start_address, m_end_address }; #endif SystemC——端口 SC_MODULE (Component) { sc_in_clk clk; sc_port ram_if int ram_port; // 实例化端口 void action ( ); int data; unsigned int address; SC_CTOR ( ) { SC_METHOD (action, clk. pos( )); } }; void Component :: action ( ){ wait ( ); int i = 0; while (i++ 100) { address = 0; if (transfer_status status = ram_port ? write (address, data)) { // 通过端口ram_port调用存储器写方法 cout Write RAM successfully endl; } SystemC——端口 else cout Write RAM fail endl; if (transfer_status status = ram_port ? read (address, data)) { // 通过端口ram_port调用存储器读方法 cout Read RAM successfully endl; } else cout Read RAM fail endl; wait( ); address++; } sc_stop( ); } TLM设计实例——简易DMA设计 DMA往往是总线的主设备，它可以发起存储器之间的数据传输 DMA也是总线的从设备，DMA中有若干个控制寄存器，当配置这些寄存器的时候DMA作为总线的从设备 DMA与总线之间有两种接口，一种是主设备接口master_if，另一种则是从设备接口slave_if 简易DMA设计——没有时钟的DMA模型 DMA.h文件如下： #ifndef _dma_h #define _dma_h #include systemc.h #include slave_if.h #include master_if.h enum state_type{idle, read_state, write_state}; SC_MODULE(dma) { //端口 public: sc_inbool rst; //初始化信号 sc_portmaster_if master_port; //总线主设备接口 sc_portslave_if slave_port; //总线从设备接口 //signal sc_signalunsigned int my_state; //用来做进程间通信 sc_signalunsigned int dma_enable; //用来做进程间通信 简易DMA设计——没有时钟的DMA模型 SC_HAS_PROCESS(dma); //macro definition //DMA构造函数，指定模块名称和模块所属的地址空间 dma(sc_module_name name_, unsigned int start_address, unsigned int end_address) : sc_module(name_) ,reg_start_address(start_address) ,reg_end_address(end_address) { // process declaration SC_THREAD(main_action); sensitive my_state; SC_THREAD(dma_fsm); sensitive my_state dma_enable; SC_METHOD(