VHDL语言介绍.pptVIP

第四章 VHDL语言 ENTITY mux21 IS PORT(a,b:IN BIT;s:IN BIT;y:OUT BIT); END ENTITY mux21; ARCHITECTURE one OF mux21 IS BEGIN y=(a AND (NOT s)) OR (b AND s); END ARCHITECTURE one; 一个可综合的vhdl描述的基本逻辑结构中：实体和结构体是必需的 实体（entity）说明 描述外部接口信息 结构体(architecture)说明 描述内部逻辑功能 [例4-2] …… ARCHITECTURE one OF mux21 IS BEGIN y = a WHEN s=0 ELSEb ; END ARCHITECTURE one; ENTITY mux21 IS PORT(a,b,s:IN BIT;y: OUT BIT); END ENTITY mux21; ARCHITECTURE one OF mux21 IS BEGIN PROCESS(a,b,s) BEGIN IF s=‘0’ THENy= a;ELSEy=b; END IF; END PROCESS; END ARCHITECTURE one; 二、VHDL相