VHDL数字电路课程实验报告知识点.docVIP

VHDL数字电路课程实验报告 实验一 8分频器 一、实验要求：分别用信号量和变量实现八分频器 二、实验过程： 1、代码： 8分频器vhd library ieee; use ieee.std_logic_1164.all; entity freq_divider is port(clk: in std_logic; out1, out2: buffer bit); end freq_divider; architecture example of freq_divider is signal count1: integer range 0 to 7; begin process(clk) variable count2: integer range 0 to 7; begin if(clkevent and clk=1) then count1=count1+1; count2:=count2+1; if(count1=3) then out1=not out1; count1=0; end if; if(count2=4) then out2=not out2; count2:=0; end if; end if; end process; end example; 八分频器tb LIBRARY ieee; USE ieee.std_logic_1164.al